In a multi-core processor system, plural CPUs run plural threads. Shared resources, such as memory and a bus, shared by the plural CPUs may be accessed concurrently by plural CPUs. Since the shared resources, for example, cannot perform processes related to plural accesses simultaneously, the shared resources judge the priority of each access and perform the processes related to the accesses in the order of priority.
A technology is known of causing in a fault-tolerant system, all CPUs to perform the same operation in a failure mode. Namely, when plural CPUs contend for access of shared resources, the plural CPUs access the same data of the shared resources. Then, to permit a master CPU to access the shared resources, to not permit a slave CPU to access the shared resources, and to return results of the access by the master CPU to the slave CPU, where a clock of a phase opposite to that of the clock to be supplied to the master CPU is supplied to the slave CPU. A technology is known of delaying the timing of the access of the shared resources by the slave CPU compared to the timing of the access by the mater CPU (see, e.g., Published Japanese-Translation of PCT Application, Publication No. 2008-518311).
The conventional technologies, however, have a problem in that when two accesses of the shared resources happen at the same time in a mode other than the failure mode, the processing related to one of the accesses is caused to wait.